1. Field of the Invention
This invention relates to an improved implementation of a Multiple Input Signature Register (MISR) for arrays employing a test scan output data register, and more particularly a combination of array output data register and MISR that reduces the number of wiring channels and overall use of critical chip area without impacting array performance.
2. Description of the Background
As will be appreciated by those skilled in the art, as the design of electronic integrated circuit chips has progressed, more and more circuitry is being disposed in increasingly dense patterns and it is becoming correspondingly more difficult to test such circuits. One methodology for performing chip test is described in U.S. Pat. No. 4,071,902, assigned to the assignee of this application and incorporated herein by reference. This patent describes the basic features of level sensitive scan design (LSSD) systems for circuit test. A further aid to device and system testing is the method called self-test. A methodology for self-test in and LSSD environment is described in U.S. Pat. No. 4,503,537 assigned to the assigned to the assignee of this application and incorporated herein by reference. Here, during test, the test scan outputs of shift register strings are fed to a so-called Multiple Input Signature Register (MISR). The signals fed to the MISR are compressed within the MISR to form a resultant or signature at the end of the test that can be compared with the expected or good signature for a pass/fail decision.
FIGS. 1A and 1B show a traditional combination of an array output register and an MISR. An array 12 has a plurality of inputs held in a series of L1/L2 input latches 14 and 16, only two of which are shown L10/L20 and L1N/L2N and a corresponding series of L1/L2 output latches 18 and 20 respectively, only two of which are shown, L10/L20 and L1N/L2N. The array 12 is, a Static Random Access Memory (SRAM), but it will be appreciated that the principles of the invention are applicable generally to digital circuit arrays. The output of the array (ARRAY DATA) is one input to the master L1 latch 18. The other inputs to latch 18 arc an array clock signal (ARRAY CLOCK), a scan in signal SCAN IN, and a scan in A clock SCAN A CLK. The output of latch 18 is fed to a listening MSIR register comprised of master (L1) latch 22 and slave (L2) latch 24 via an XOR gate 26, whose other input is an MISR P bit indicating the binary state of different combination of master slave output register latch and a MISR for signature capture in the MISR. The master/slave registers 22 and 24 can be scan initialized with the SCAN A clock and SCAN B clock respectively. The scan output of the master slave latch 18/20 is fed to the scan in of the master/slave latch 22/24. This implementation needs two sets of master/slave latches, the output L1/L2 latch 18/20 and the MISR L1/L2 latch 22/24, and the XOR gate 26. This logic at the output of the array requires a number of wiring channels requires the use of critical area on the chip.